Enabling VLSI processing blocks for MIMO-OFDM Communications

Multi-input multi-output (MIMO) systems combined with orthogonal frequency-division multiplexing (OFDM) gained a wide popularity in wireless applications due to the potential of providing increased channel capacity and robustness against multipath fading channels. However these advantages come at the cost of a very high processing complexity and the efficient implementation of MIMO-OFDM receivers is today a major research topic. In this paper, efficient architectures are proposed for the hardware implementation of the main building blocks of a MIMO-OFDM receiver. A sphere decoder architecture flexible to different modulation without any loss in BER performance is presented while the proposed matrix factorization implementation allows to achieve the highest throughput specified in the IEEE 802.11n standard. Finally a novel sphere decoder approach is presented, which allows for the realization of new golden space time trellis coded modulation (GST-TCM) scheme. Implementation cost and offered throughput are provided for the proposed architectures synthesized on a 0.13  CMOS standard cell technology or on advanced FPGA devices

Técnicas y trazado frente a la artillería, el caso del fuerte de Santa Cruz en Orán- Argelia

The fort of Santa Cruz, Built between the XVI and the XVIII century, is an interesting example of the modern bastioned fortification built by the Spanish Crown in Oran (Algeria), and the main one of the most important defense system in North Africa. Its construction was progressive, following the different projects proposed by famous engineers sent by the Spanish Crown. These projects were designed to reinforce and defend its most exposed front to the Ottoman attacks, using designs and constructive methods to face the enemy’s artillery from the XVI to the XVIII century. Afterwards, and during the French occupation Santa Cruz was restored after being destructed by the Spaniards, as was stated in the treaty between the Bey of Algiers Hassan Pacha and the Spanish Royalty Carlos IV. In this communication we will analyse the choices of the design and the constructive methods used to slow down the devastating effects of the artillery against the main front of Santa Cruz by the Spaniards after the recapture of the city in 1732

Hardware architecture for matrix factorization in MIMO receivers

This paper presents the hardware realization of the factorization algorithm required in a MIMO OFDM receiver to make the detection and decoding a non-orthogonal space-time code. Requirements of a real scenario represented by the standard IEEE 802.11n for WLAN have been analyzed and exploited to draw out the specifications of the proposed implementation. A very high throughput hardware realization has been obtained able to factorize 128 8x8 real channel matrices during the channel updating period of 28 &3956;s, with a final throughput of 4,63 millions of matrices processed per second. Synthesis results on both 0.13 &3956;m CMOS standard cell technology and FPGA compare favourably to previous implementations

Decoding the Golden Code: a VLSI design

The recently proposed Golden code is an optimal space-time block code for 2x2 multiple-input-multiple-output (MIMO) systems. The aim of this work is the design of a VLSI decoder for a MIMO system coded with the Golden code. The architecture is based on a rearrangement of the sphere decoding algorithm that achieves maximum-likelihood (ML) decoding performance. Compared to other approaches, the proposed solution exhibits an inherent flexibility in terms of QAM modulation size and this makes our architecture particularly suitable for adaptive modulation schemes. Relying on the flexibility of this approach two different architectures are proposed: a parametric one able to achieve high decoding throughputs ( >165 Mb/s) while keeping low overall decoder complexity (45 KGates), a flexible implementation able to dynamically adapt to the modulation scheme (4-,16-,64-QAM) retaining the low complexity and high throughput features